Hybrid bonding, the protagonist of the future!

Wafer bonding is an emerging semiconductor processing technology that has developed rapidly in recent decades. It has important applications in MEMS, CIS and memory chips, and has received more and more attention.

In the ocean of information, the presence of wafer bonding is extremely thin compared to lithography, but when we take out a phone, its image sensor, gravity acceleration sensor, microphone, 4G and 5G RF front ends, and part of NAND, all are more or less applied to wafer bonding technology. It can be said that the wafer bonding technology has made an important contribution to our information life.

01 Bond = bond

 Wafer bond (wafer bonding) is distinguished by name from the lead bond wire bonding and patch bond die bonding applied in the traditional package. In Japanese, bonding is translated as engagement, which makes it easier to understand this process and process from the intuitive impression.

 In terms of the bonding mode, the wafer bonding can be divided into * bonding and temporary bonding. The difference, as the name suggests, * bonding requires no need to unbond (debonding), while temporary bonding also needs to unbond to reopen the combined wafers.

 In terms of interface materials, it is divided into glue bonding with intermediate layer, common crystal bonding, metal thermal pressure bonding, melting bonding (fusion bonding) and anode bonding without intermediate layer.

 The purpose of the bonding also varies, Such as providing airtight protection for the devices, Some application scenarios in MEMS and SAW; Such as providing mechanical support or layer transfer for thinning wafers, For example, the application in IGBT and BSI is based on this purpose; The latest and most important application is the three-dimensional interconnection of transistors, HBM, 3D NAND, the complementary field-effect transistor CFET and back power supply network BPN under development, The rise of hybrid bonding (hybrid bonding) in recent years is a process focused at this application, The process is named for its inclusion of both melting bonding and metal bonding features.

Early wafer bonding is not high enough to control the accuracy of the sleeve engraving, and it can be within 10 microns after bonding. However, since the beginning of BSI, the precision requirement has reached the level of 1.5 micron, and for the application of 3D NAND and high-end BSI, it has reached the requirement of below 300 nm or even 150 nm! With the development of bonding technology and the penetration of the forward process, the author boldly speculated that in the future.

02 Old wine in new bottles

 As previously mentioned, the essence of bonding is bonding, and the principle of joining two different interfaces using a variety of different physical and chemical ways has been discovered and applied as early as before humans cut out * wafers. Whether it is glue bonding with polymer compounds, cocrystal bonding by welding principle, or even melting bonding by van der Waals force between ultra-smooth surfaces, the basic principle was known before the birth of wafer bonding. But the real large-scale industrial applications of wafer bonding only began in the last decade.

 In 1969, Wallis and Pomerantz * described the bonding of silicon experience with electric fields at 500℃, the anode bonding today.

 In 1986, IBM and Toshiba found fusion bonding in their research. When the silicon wafer was specular polished, it could be bonded by van der Waals forces without other adhesive media, which is the beginning of direct silicon-silicon bonding. In the following years, fusion-bonding techniques for SOI, MEMS, and family III-V compounds were successively published successively. After the 1990s, normal temperature bonding + low temperature annealing and melting bonding under high vacuum have been developed.

 In 2016, SONY first produced image sensors using hybrid copper-silica bonding. The idea, which began in the mid-1980s, finally became a reality after a decade of research and was accepted by the industry.

 There are many ways of three-dimensional interconnection through wafer bonding, but as with the fusion bonding scheme shown in (a) and the hybrid bonding scheme shown in (d), it is more suitable for advanced CMOS processes.

 Metal hot pressure bonding (c) need to use extremely high pressure (10-100 kN), even similar anode bonding will use high voltage electric field, for CMOS process compatibility is not so friendly, easy to destroy the front metal pattern, so only need the normal temperature bonding + low temperature annealing melting bonding and mixed bonding (d) because of its good process compatibility with CMOS, get more and more favor.

 Melting bonding is not born so mild, from the early need 1000℃ high temperature annealing process conditions, developed to only atmospheric plasma surface activation after normal temperature bonding, under the condition of less than 400℃ annealing, even under the ultra-high vacuum using plasma surface activation without annealing, for its powerful CMOS process compatibility. The hybrid bonding of interconnection directly using copper contacts without the help of TSV reduces the interconnection distance between the upper and lower wafers to the shortest, further improving the electrical performance.

Thanks to the rapid development of melting bonding and mixing bonding, the obstacle of wafer bonding to CMOS interconnection process have been removed.

03 Melting bonding: from SOI to BSI

 Melting bonding is usually silicon-silicon or silicon-silica as the bonding interface, after appropriate surface treatment. I have seen a saying that as long as the surface is smooth and smooth enough, everything can be bond, so special substrates such as indium phosphide and lithium niobate can also be fused and bonded with silicon wafers!

 Early relatively known applications of fusion bonding were for the production of silicon on SOI insulators. As a substrate material with rich optical and electrical properties, the preparation of SOI is also naturally more complex than the conventional silicon wafers. Bare silicon wafer and thermal oxygen wafer are thinner on the back, which is the main preparation method of SOI sheet in the early stage after melting and bonding. However, due to their high cost, slow production speed and poor uniformity, their application scenarios are relatively limited. Later, the SmartCut® technology developed by Soitec in France has improved the cost, production speed and uniformity index. The naked silicon wafer as the donor wafer automatically breaks through hydrogen ion injection, separating the donor wafer, which can be reused after surface polishing.

 The more well-known application for fusion bonding is for the production of BSI backshot image sensors. In the initial BSI, the CMOS back was thinned to make the pixel array. With the development of the demand for image signal processing, it has become a new way to melt and bond the logical wafer of image processing with CMOS wafer face to face and connect it with TSV. When the technology of hybrid bonding matured, BSI also entered the era of high-density interconnection, which is later.

In addition, I have also seen cases of using fusion bonding to connect chips such as micro LED and MEMS with CMOS in some papers. Including IMEC's CFET technology route, there are also applications that use melting bonding to make 3 D transistors. With the advent of the semiconductor 3 D era, the potential of melting bonding is inestimable.

04 Hybrid bonding: New era business card

When it comes to the most typical application of hybrid bonding, there is no doubt that the Xtacking® of Changjiang Storage. Through different processes, Memory wafer and CMOS wafer are made successively, and the two contacts are built in the back process process. Through hybrid bonding, these contacts are linked through, and Memory and CMOS are interconnected in the vertical direction.

According to the Frauebhofer Institute, there are three advantages of hybrid bonding:

Shorter interconnection distance: not only does not need to connect to each other with leads, but also does not need to cross the whole CMOS layer with TSV, which can be connected only by connecting the copper contacts of the rear channel

Higher interconnection density: The area of the copper contact is very small, and the copper contact in the hybrid bonding process has less than 10 microns pitch size than the TSV of 100 microns, which can undoubtedly achieve a higher interconnection density

 Lower cost: There is no doubt that it takes more time to interconnect for each DIE alone. Large area and high density interconnection can be achieved through wafer bonding, and the contribution to the improvement of production capacity is a leap forward! Naturally, production costs can also be reduced

 In addition to the previously mentioned BSI, cases such as micro LED and CMOS for mixed bonding also exist. In the latest study, there are even micro LED made on a small size wafer, cut into independent DIE and re-bonded to a 12-inch wafer and CMOS 12 inch wafer for hybrid bonding and interconnection, which shows that its process compatibility is very excellent. This is another big advantage of hybrid bonding. The CMOS of different technology nodes can also be connected through copper contacts, and the flexibility of process selection is also improved by a leap forward!

Of course, the hybrid key combination is non- *, for example, the failure DIE cannot be known from the initial stage, only after the integration, thinning and slice and through the test, so the yield of the finished DIE will be greatly affected. Secondly, the bonding interface requires super high flatness, and the internal stress of the wafer also needs to be controlled to reduce the warping of the wafer, which puts forward harsh requirements for the control of the posterior process. Compared with the traditional packaging technology, the cleanliness level of ISO3 required for hybrid bonding is much higher than the cleanliness requirement of ISO5 in the traditional sealing and testing plant, and high requirements are put forward for the control of factory affairs and environment.

05 * Players

 The implementation of the process need to rely on the support of materials and equipment, although is after process, but the player is rare, including from Germany (Karl Suss) and Austria EVG (EV Group), Japan's Canon and mitsubishi although also have special categories of bonding equipment, but both market share and technical level cannot with the two * players. At present, the information of wafer bonding in China is "wafer bonding Manual", in which the equipment of Suss and EVG is quite high and has been repeatedly mentioned, and its popularity and status are self-evident.

 Seuss and EVG's product lines have a high coincidence degree, covering almost all types of bonding processes at the same time. In addition to bonding machines, there are also alignment machines for wafer alignment and double-sided lithography machines, as well as the measuring machine to detect bonding accuracy, but in fact each has its own merits. In the domestic bonding machine market, compared with EVG, Seuss has a better reputation and market share in universities and research institutes, but EVG is better in industrial applications. Especially in the domestic advanced BSI production line, EVG's fully automatic melt bonding machine GeminiFB has almost reached 100% of the market share!

At present, the domestic bonding machine is still mainly low-end. Although the bonding machine developed and produced by Shanghai S Company has penetrated into the market of glue bonding and metal bonding, it has not yet entered the main position of melting bonding. Another domestic enterprise focusing on bonding machine is H Company. Like S Company, H Company is known as its lithography subsystem. Its 200nm alignment accuracy is not comparable to the previous generation of EVG products, but it is also a major breakthrough for local enterprises! In addition, there are several semiconductor equipment manufacturing companies are developing new bonding equipment, after all, until last year, the growth of the CIS industry has lasted for 10 years, the market space is quite broad! While the CIS market fell for the first time in 2022, the CIS market is large enough to accommodate players outside Suss and EVG as demand for security and SG continues.

06 is written at the end

 In the past decade, the pace of advancing Moore's Law has gradually slowed down, and more and more semiconductor companies seek advanced packaging to drive the improvement of chip performance, heterogeneous integration is one solution, and the wafer bond process provides an efficient realization path, become a powerful candidate process!

When Intel and IMEC announced the future transistor development route in 2022, and entered the CFET era after 1nm, I was convinced that fusion bonding and hybrid bonding will move from the back to the front, and lead the next 15 years of semiconductor industry development together with high NA and hyper NA EUV lithography machines!